DMA: preallocated 2048 KiB pool for atomic coherent allocations VFP support v0.3: implementor 42 architecture 4 part 00 variant 0 rev 0 Setting up static identity map for 0x5746f0 - 0x574748 Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes) Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) Calibrating delay loop (skipped), value calculated using timer frequency. sched_clock: 56 bits at 27MHz, resolution 37ns, wraps every 2545165795328ns Architected cp15 timer(s) running at 27.00MHz (virt). irq_brcmstb_l2: registered L2 intc (mem: 0xfc4d1200, parent irq: 57) irq_brcmstb_l2: registered L2 intc (mem: 0xfc410640, parent irq: 97) irq_brcmstb_l2: registered L2 intc (mem: 0xfc441000, parent irq: 74) irq_brcmstb_l2: registered L2 intc (mem: 0xfc403000, parent irq: 95) RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2. Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) Kernel command line: root=/dev/mmcblk0p4 rootwait rw rootflags=data=journal debug coherent_pool=2M 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes) Built 1 zonelists in Zone order, mobility grouping on. HighMem zone: 329728 pages, LIFO batch:31 HighMem zone: 4624 pages used for memmap Normal zone: 194560 pages, LIFO batch:31 free_area_init_node: node 0, pgdat c07e77c0, node_mem_map cd6f6000 CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache CPU: ARMv7 Processor revision 3 (ARMv7), cr=30c7387d